1. Field of the Invention
The present invention relates to charge pump circuits. In particular, the present invention is an integrated, zero hold current and delay compensated charge pump.
2. Description of the Prior Art
Charge pumps are commonly used circuits for controlling current flow. Digitally controlled charge pumps are often found in phase locked loops where they are used to control the sourcing of current into and sinking current from a filter coupled to the control input terminal of the voltage controlled oscillator. When operated in its charge-up mode, the charge pump will provide current to the filter thereby increasing the voltage on the filter and the frequency of the voltage controlled oscillator. When operated in its charge-down mode, the charge pump will draw current from the filter, thereby decreasing its voltage and the frequency of the voltage controlled oscillator. In its hold mode, the charge pump is essentially isolated from the filter. With current being neither drawn from nor supplied to the filter, its voltage and therefore the frequency of the voltage controlled oscillator are maintained at a steady state.
FIG. 1 is a schematic illustration of a known charge pump. The charge pump shown in FIG. 1 includes current sources 1, 2, and 3, and two emitter coupled pairs of transistors 4 and 5, and 6 and 7. Currents I1-I3 of the same magnitude are provided by current sources 1-3. This prior art charge pump is operated in a charge-up mode when logic HIGH, LOW charge-up signals are applied to the UP and UPN terminals and logic LOW, HIGH charge-down signals are applied the DN and DNN terminals, respectively. Transistor 4 will be turned ON and conduct current I2, while transistor 6 will be turned ON and conduct current I3. Since transistors 5 and 7 are turned OFF, current I1 is supplied or sourced to output terminal I.sub.0. When the logic states of the signals are reversed (i.e. logic LOW, HIGH charge-up signals are applied to terminals UP and UPN, and logic HIGH, LOW charge-down signals are applied to terminals DN and DNN, respectively), transistors 4 and 6 are turned OFF while transistors 5 and 7 are turned ON. Both currents I2 and I3 will thereby be drawn from the node joining current source 1 to the collectors of transistors 5 and 7, while only current I1 is supplied to this node. Since the magnitude of currents I1, I2, and I3 are equal, an additional current will be sinked or drawn from output terminal I.sub.0.
The charge pump shown in FIG. 1 is operated in its hold mode when the UP and UPN terminals receive charge-up signals having logic LOW and HIGH states, while the charge-down signals have logic LOW and HIGH states applied to the DN and DNN terminals, respectively. Transistors 5 and 6 are turned OFF, while transistors 4 and 7 are switched ON by these signals. Current I1 is thereby conducted through transistor 7, while current I2 is conducted through transistor 4. In theory current will be neither sourced to nor sinked from output terminal I.sub.0 since currents I1 and I2 are of equal magnitude. When the charge-up and charge-down control signals are synchronized in time, no current will be output from the charge pump since the switching is very symmetrical, being performed differentially using NPN transistors 4-7.
In practice, however, the hold current is not zero when the charge pump is operated in its hold mode. A small amount of current will either flow to or be drawn from the output terminal of the charge pump. This can be a problem when the charge pump is used to control a phase lock loop, since it will lead to large amounts of steady-state error. Typically, the values of currents I1 and I2 are laser trimmed so that when the pump is in a hold state, very little current comes from the output terminal. The accuracy of this trimming operation can be to within plus or minus 0.1 percent. However, in many applications this will not result in a low enough hold current. Additionally, as supply voltages VCC and VEE vary, the hold current will get larger due to the mismatch of currents caused by the Early effect of the transistors. This effect is unavoidable with this type of pump.
Other current switching circuits are also known. The Jadus et al. U.S. Pat. No. 4,331,887 discloses current switch driving circuitry for supplying current to an output terminal. The output terminal is connected between a driving transistor and a sinking transistor. The driving and sinking transistors are coupled by logic signals applied to an ON control terminal, and an OFF control terminal. When both the ON and OFF control terminals are switched to a HIGH logic state, both driving and sinking transistors are switched OFF, preventing the output terminal from either sourcing or sinking current. The current will be sourced out of the output terminal when the ON control terminal is switched to a LOW logic state, and the OFF control terminal is switched to a HIGH logic state. When the OFF terminal is switched to a LOW logic state and the ON terminal is switched to a HIGH logic state, the sinking transistor is turned ON, and will draw current through the output terminal.
The Heimbigner U.S. Pat. No. 4,363,978 discloses a tristate driver circuit. The driver includes an output driver formed by two FETs having their source and drain terminals connected in series between a relatively positive potential V.sub.DD and a relatively negative potential V.sub.SS. An output terminal is connected between the two transistors. The output driver is controlled by two NOR gates formed by several FETs, as well as by other FETs. A buffer is driven to its float mode, or tristated, when the F terminal and F(bar) terminal receive logic 1 and logic 0 signals, respectively. The transistors of the output driver are then turned OFF.
The Takada U.S. Pat. No. 4,259,599 discloses a complementary transistor switching circuit. Either one or the other of two complementary transistors is turned OFF regardless of the state of the drive transistor. The other transistor will be turned ON.
The Backes et al. U.S. Pat. No. 4,633,106 discloses an MOS bootstrap push-pull stage which uses a diode capacitor charge pump.
The Sud et al. U.S. Pat. No. 4,570,244 discloses a transistor capacitor charge pump which is turned ON and OFF with clock pulses.
It is evident that there is a continuing need for improved charge pumps. A charge pump having a zero hold current as well as symmetrical switching characteristics is desired. A charge pump having these characteristics which can operate at several different pumping currents would also be useful. The circuit must of course be relatively simple if it is to be commercially viable.